Photonic chip layout
is the
bottleneck
everyone is about to hit.
Lunima is a photonic design environment. Physics-informed generative models lay down a working circuit in minutes; a full editing layer lets your engineers explore, constrain and refine it — in real microns, against real loss.
PIC complexity is doubling every 18 months. Layout productivity is essentially flat.
Component counts on a single die have crossed ten thousand. Most layout work is still authored by hand — placed component by component, routed waveguide by waveguide, tuned bend by bend by an engineer with a mouse.
Every crossing is a loss.
Every bend is a loss.
Every nm of detour is a loss.
A photonic die does not forgive bad geometry. Optical penalty compounds.
Electronic CAD treats geometry as topology.
Photonics treats geometry as physics.
A copper trace can turn 90 degrees and electrons follow. A waveguide cannot. Its path radiates a wavelength-scale electromagnetic mode whose loss, phase, crosstalk and polarization depend on every micron of the shape it cuts through silicon. You cannot abstract the geometry away from the field it carries.
Topology preserved.
Geometry abstracted.
Sign-off via DRC.
Geometry is the device.
Bend radius is physics.
Sign-off via simulation.
A generative model that draws inside the physics it has to satisfy.
Structural priors
The model has been shown the geometry of every layout class that ships at volume — from MZIs and AWGs through resonator banks and coherent transceivers.
Physical loss inside the loop
Bend loss, mode mismatch, crossing penalty, thermal coupling and PDK rules are differentiable terms — not post-hoc checks.
Constraint-aware sampling
We don't generate then filter. We generate inside the manifold of manufacturable solutions, parameterized by your PDK.
An editing environment, not a black box
The model proposes a full layout in minutes. You stay in control — explore alternatives, lock regions, redraw by hand and refine in real microns, then export to the fab flow you already run.
What takes days of manual layout to draw, Lunima drafts in minutes.
Layouts come out close to hand-optimized references, competitive on footprint, and clean against partner PDKs — a working draft your team refines in the editor, not a black box you have to trust.
| INSERTION LOSS | close to hand-optimized references |
|---|---|
| CROSSTALK | low — optimized inside the loop |
| FOOTPRINT | competitive with expert layout |
| DRC | clean against partner PDKs |
| HANDOFF | export to the fab flow you already run |
Built by photonics, ML and EDA engineers who have experienced the problem first hand.
The team has background in ML, AI, and photonics. We have a team of ex-FAANG engineers and photonics researchers advised by professors at the top of their field.
- PRIOR WORK
- PRINCETON, AMAZON, AKHTONICS
- STAGE
- Seed · 2026
- LOCATION
- PRINCETON, NJ